Chromite M Soc Manual¶
Welcome to the ChromiteM SoCs documentation. The source code of the SoC is available at: https://gitlab.com/incoresemi/fpga_ports/chromitem_soc
Copyright (c) 2020, InCore Semiconductors Pvt. Ltd.
Information in this document is provided “as is” with faults, if any.
InCore expressly disclaims all warranties, representations, and conditions of any kind, whether express or implied, including, but not limited to, the implied warranties or conditions of merchantability, fitness for a particular purpose and non-infringement.
InCore does not assume any liability rising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation indirect, incidental, special, exemplary, or consequential damages.
InCore reserves the right to make changes without further notice to any products herein.
- 1. Introduction
- 2. Memory Map
- 3. Getting Started
- 4. FPGA pin mapping
- 5. OS Ports
- 6. Core Pipeline
- 7. Modes of Operation
- 8. Custom CSRs
- 9. Physical Memory Protection (PMP)
- 10. Performance Monitors
- 11. L1 Cache Subsytem
- 12. Interrupts
- 13. Debug
- 14. Debug Interface
- 15. Boot Config
- 16. General Purpose Input Output Controller
- 17. Core Local Interrupt (CLINT)
- 18. Platform Level Interrupt Controller (PLIC)
- 19. Universal Asynchronous Receiver/Transmitter (UART)
- 20. Licensing and Support