17. Core Local Interrupt (CLINT)

This chapter will provide details on the Core Local Interrupt (CLINT) controller instantiated in this design. CLINT is responsible for maintaining memory mapped control and status registers which are associated with the software and timer interrupts. The spec presented here is compatible with the RISC-V Privileged Architecture Version 1.10

17.1. IP Details and Available Configuration

Table 17.1 provides details of the source of the IP and and details of the memory map.

Table 17.1 CLINT IP details

Value

Provider

gitlab

Vendor

incoresemi

Library

blocks/devices

Version

1.1.2

Ip Type

memory_mapped

Numer of Config Registers

3

Direct Memory Region

None

Configuration Register Alignment (bytes)

8

Table 17.2 provides information of the various parameters of the IP available at design time and their description

Table 17.2 CLINT IP Configuration Options

Configuration

Options

Description

Bus interfaces

APB, AXI4L, AXI4

Choice of bus interface protocol supported on this IP

Base address

Integer

The base address where the memory map of the configuration register starts

Bytes reserved

Integer >= 0XBFFF

The number of bytes reserved for this instance. This can be much larger than the actual bytes required for the configuration registers but cannot be smaller than the value indicated.

tick_count

Integer > 1

defines the number of clocks cyles required to increment the mtime register by 1.

msip

Integer > 1 and < 32

defines the size of the msip register. Each bit is typically required to interrupt a separate hart

17.2. CLINT Instance Details

Table 17.3 shows the values assigned to parameters of this instance of the IP.

Table 17.3 CLINT Instance Parameters and Assigned Values

Parameter Name

Value Assigned

Base Address

0X2000000

Bound Address

0X200BFFF

Bytes reserved

0XBFFF

Bus Interface

AXI4L

tick_count

0X100

msip

0X1

17.3. Register Map

The register map for the CLINT control registers is shown in Table 17.4.

Table 17.4 CLINT Register Mapping for all configuration registes

Register-Name

Offset(hex)

Size(Bits)

Reset(hex)

Description

msip

0X0

1

0X0

This register generates machine mode software interrupts when set.

mtimecmp

0X4000

64

0X0

This register holds the compare value for the timer.

mtime

0XBFF8

64

0X0

Provides the current timer value.

All addresses not mentioned in the above table within Base Address and Bound Address are reserved and accesses to those regions will generate a slave error on the bus interface

The register access attributes for the CLINT control registers are shown in Table 17.5.

Table 17.5 CLINT Register Access Attributes for all configuration Registers

Register-Name

Access Type

Reset Type

Min Access

Max Access

msip

read-write

synchronous

1B

8B

mtimecmp

read-write

synchronous

1B

8B

mtime

read-write

synchronous

1B

8B

Table 17.6 captures the side-effects caused to either reads or writes on certain registers.

Table 17.6 CLINT Register Side Effects

Register-Name

Read Side Effects

Write Side Effects

mtimecmp

none

Writing to register clears the timer interrupt.

Note

Registers not included in the Side Effects table have no side-effects generated either on a read or a write.

17.4. MSIP Register

Machine-mode software interrupts are generated by writing to the memory-mapped control register msip . The msip register is a 32-bit wide WARL register where the upper 31 bits are tied to 0. The least significant bit can be used to drive the MSIP bit of the mip CSR of a RISC-V hart. Other bits in the msip register are hardwired to zero. On reset, the msip register is cleared to zero.

17.5. MTIMECMP Register

This is a read-write register and holds a 64-bit value. A timer interrupt is pending whenever mtime is greater than or equal to the value in the mtimecmp register. The timer interrupt is used to drive the MTIP bit of the mip CSR of a RISC-V core.

17.6. MTIME Register

mtime is a 64-bit read-write register that keeps track of the number of cycles counted from an arbitrary point in time. It is a free-running counter which is incremented every tick_count number of cycles

17.7. IO and Sideband Signals

Table 17.7 CLINT generated side-band signals generated

Signal Name (RTL)

Size

Direction

Description

sb_clint_msip

1

output

Drive the MSIP bit in mip CSR of corresponding RISC-V cores. Indicates a software interrupt is pending.

sb_clint_mtip

1

output

Drive the MTIP bit in mip CSR of RISC-V cores. Indicates a timer interrupt is pending.

sb_clint_mtime

64

output

Holds the current value of the mtime register. Used as a shadow for TIME csr in a RISC-V core.