Chromite M Soc Manual¶
Welcome to the ChromiteM SoCs documentation. The source code of the SoC is available at: https://gitlab.com/incoresemi/fpga_ports/chromitem_soc
Note
Proprietary Notice
Copyright (c) 2020, InCore Semiconductors Pvt. Ltd.
Information in this document is provided “as is” with faults, if any.
InCore expressly disclaims all warranties, representations, and conditions of any kind, whether express or implied, including, but not limited to, the implied warranties or conditions of merchantability, fitness for a particular purpose and non-infringement.
InCore does not assume any liability rising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation indirect, incidental, special, exemplary, or consequential damages.
InCore reserves the right to make changes without further notice to any products herein.
- 1. Introduction
- 2. Memory Map
- 3. Getting Started
- 4. Supported FPGAs
- 5. OS Ports
- 6. Core Pipeline
- 7. Modes of Operation
- 8. Custom CSRs
- 9. Physical Memory Protection (PMP)
- 10. Performance Monitors
- 11. L1 Cache Subsytem
- 12. Interrupts
- 13. Debug
- 14. Debug Interface
- 15. Boot Config
- 16. General Purpose Input Output Controller
- 17. Core Local Interrupt (CLINT)
- 18. Platform Level Interrupt Controller (PLIC)
- 18.1. IP Details and Available Configuration
- 18.2. PLIC Instance Details
- 18.3. Register Map
- 18.4. PLIC Interrupt Priorities
- 18.5. PLIC Interrupt Pending Bits
- 18.6. Interrupt Enables
- 18.7. Interrupt Thresholds
- 18.8. Interrupt Claim Process
- 18.9. Interrupt Completion
- 18.10. IO and Sideband Signals
- 18.11. PLIC Interrupt Mapping
- 19. Universal Asynchronous Receiver/Transmitter (UART)
- 19.1. IP Details and Available Configuration
- 19.2. UART Instance Details
- 19.3. UART Features
- 19.4. Register Map
- 19.5. BAUD Register
- 19.6. TX_DATA Register
- 19.7. RX_DATA Register
- 19.8. STATUS Register
- 19.9. CONTROL Register
- 19.10. STATUS_CLEAR Register
- 19.11. INTERRUPT_EN Register
- 19.12. IO and Sideband Signals
- 20. Pulse Width Modulation (PWM) Module
- 21. Licensing and Support