Chromite M SoC Manual
0.9.1
Chromite M SoC
v: 0.9.1
Release Versions
latest
stable
0.9.1
0.9.0
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1. Introduction
2. Memory Map
3. Getting Started
4. FPGA pin mapping
5. OS Ports
5.1. Zephyr
6. Core Pipeline
7. Modes of Operation
8. Custom CSRs
9. Physical Memory Protection (PMP)
10. Performance Monitors
11. L1 Cache Subsytem
12. Interrupts
13. Debug
14. Debug Interface
15. Boot Config
16. General Purpose Input Output Controller
17. Core Local Interrupt (CLINT)
18. Platform Level Interrupt Controller (PLIC)
19. Universal Asynchronous Receiver/Transmitter (UART)
20. Licensing and Support
Chromite M SoC Manual
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5. OS Ports
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5. OS Ports
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5.1. Zephyr
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A Zephyr port of the current SoC can be found here:
https://gitlab.com/incoresemi/os_ports/zephyr
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Chromite M SoC
v: 0.9.1
Release Versions
latest
stable
0.9.1
0.9.0
Quick Links
Project Home
Releases