Chromite M SoC Manual
stable
Chromite M SoC
v: stable
Release Versions
latest
stable
0.10.0
0.9.9
0.9.6
0.9.5
0.9.1
0.9.0
sphinx-fix
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1. Introduction
2. Memory Map
3. Getting Started
4. Supported FPGAs
5. OS Ports
5.1. Zephyr
6. Core Pipeline
7. Modes of Operation
8. Custom CSRs
9. Physical Memory Protection (PMP)
10. Performance Monitors
11. L1 Cache Subsytem
12. Interrupts
13. Debug
14. Debug Interface
15. Boot Config
16. General Purpose Input Output Controller
17. Core Local Interrupt (CLINT)
18. Platform Level Interrupt Controller (PLIC)
19. Universal Asynchronous Receiver/Transmitter (UART)
20. Pulse Width Modulation (PWM) Module
21. Serial Peripheral Interface (SPI) Module
22. QUAD Serial Peripheral Interface (QSPI) Module
23. Licensing and Support
Chromite M SoC Manual
Docs / 0.13.1
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5.
OS Ports
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5.
OS Ports
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5.1.
Zephyr
¶
A Zephyr port of the current SoC can be found here:
https://gitlab.com/incoresemi/os_ports/zephyr
.
Chromite M SoC
v: stable
Release Versions
latest
stable
0.10.0
0.9.9
0.9.6
0.9.5
0.9.1
0.9.0
sphinx-fix
Quick Links
Project Home
Releases